The invention relates to a video signal processing circuit for processing an interlaced video signal, comprising a motion-adaptive selection circuit operable by means of a decision circuit, which selection circuit has three inputs coupled to a video signal source for applying video signals thereto corresponding substantially to three position-sequential lines of two fields, and an output.
A video signal processing circuit of the type described above designed as a line number doubler is known from Radio Mentor Elektronik, No. 5, 1975, page 196. In this circuit a first input of the selection circuit is coupled directly to the video signal source, a second input is coupled to the video source through a delay circuit having a delay of one line period and a third input is coupled to the video source through a delay circuit having a delay of one field period minus half a line period. The output of the selection circuit is coupled through a line number doubler to an input combination of a change-over switch, a further input combination of which is coupled to the video signal source through a further line number doubler. The selection circuit includes an adder circuit coupled to the first and second inputs thereof, while an output of this adder circuit is connected to an input of a change-over switch, a further input of which is coupled to the third input of the selection circuit and an output is coupled to the output of the selection circuit. The changeover switch of the selection circuit is operated by means of a movement detector circuit serving as a decision circuit, which detection circuit compares the video signals of two sequential pictures supplied by the video signal source. The selection circuit which can only be used for the said application serves to obtain lines to be added from the previous field, which lines are located between the original lines of a field in the case of still pictures, or from the same field from the adder circuit serving as an interpolation circuit in the case of moving pictures.